Integrated circuits with multiple processors, known by the abbreviation MP-SoC (for “Multiprocessor System-on-Chip”), are formed on a single monolithic chip and offer very high processing capacities owing to the sharing of the tasks that can be accomplished by the various processors. The processors operate in communication with one another and the tasks are shared according to the application. The tasks are executed sequentially or in parallel, or both at the same time. Each application defines an operational program for all or part of the processors, and also defines exchange links between the various processors depending on the tasks to be accomplished.
Technological advances tend to increase the number of processors that can be placed on a chip. This number can reach several tens, or even several hundreds.
Among the problems arising during the operation of the chip, there is notably the problem of the dissipation of heat and the problem of the synchronization of the tasks being executed in order to minimize overall processing time. With regard to the dissipation of heat, local overheating of certain processors and also overall overheating of the chip need to be avoided. As far as the synchronization of the tasks is concerned, it is desirable to avoid too fast a production of results by a processor whereas another processor, waiting for these results in order to perform its own task, is not capable of processing it at the same rate; and conversely, it is desirable to avoid a processor waiting for results coming from another processor running at too slow a speed. Another parameter that is significant for the performance of the circuit can be a characteristic time, known as the “latency time”, which represents the time needed for the processor (where it is the latency time of the processor) or an assembly of processors (where it is the latency time of an assembly of processors) to supply the result of a calculation after having received the input data required for this calculation.
The operation of the chip may be optimized at the design stage of the chip, by taking into account the questions of thermal dissipation and synchronization at this design stage. But this is not compatible with the fact that the operating conditions during a real execution will, to a large extent, depend on the application and that the operation cannot be optimized for all the applications that may be envisioned.
A solution already proposed is to monitor the risks of hot spots in the chip and to reconfigure the distribution of the tasks between the processors depending on the hot spots, estimated or measured, for example by transferring a power-hungry task from one processor to another processor, during the operation.